The present invention relates to graphic accelerators, and more particularly to generating CRT timing signals in a graphics accelerator.
Computer processing of 3D (three-dimensional) graphics can be considered as a three stage pipeline, comprising the general steps of tessellation, geometry, and rendering. The tessellation stage typically refers to the creation of a description of an object and the conversion of the description to a set of triangles. The geometry stage involves transformation, i.e., the scaling and rotation of the triangles, and lighting, i.e., the determination of the brightness, shading and texture characteristics of each triangle. The rendering stage involves the calculation of all attributes of the pixels forming the triangles, e.g., color, light, depth, and texture, and provides a two dimensional display from the triangles created in the geometry stage.
In the rendering stage, data is normally processed pixel by pixel. A rendering engine calculates all attributes of the pixel (color, light, depth, and texture) and must be able to process millions of polygons per scene and to construct a quality 2D (two-dimensional) representation in real time, for animation.
In displaying graphics data on a display device, such as a CRT device, a CRT controller is utilized to provide the display signals to the display device. FIG. 1 illustrates a prior art approach for providing CRT timing signals of horizontal synchronization (Hsync), vertical synchronization (Vsync), blanking, and display enable (Disp). A horizontal counter 100 provides a horizontal line/pixel count value and a vertical counter 102 provides a vertical line/pixel count value. Separate registers 104, 106, 108, 110, 112, 114, 116, and 118 store start and end count values for the timing signals Hsync, Vsync, blanking, and display enable. The horizontal count value from horizontal counter 100 is compared with the Hsync start and end times, blanking start and end times, and display start and end times from respective registers 104, 106, 112, 114, 116, and 118 via comparators 120, 122, 124, 126, 128, and 130. The vertical count value from vertical counter 102 is compared with the Vsync start and end times from registers 108 and 110 via the comparators 132 and 134. SR flips flops 136 are set and reset based on the comparison match signals generated from the comparators 120, 122, 124, 126, 128, 130, 132, and 134 to provide the desired signaling of Hsync, Vsync, blanking, and display enable. The use of separate comparators and registers for each start and end time ensures that timing signals, which need to be generated at the same count value, are capably produced from the conventional CRT timing signal generator. Unfortunately, the logic required for the multiple comparators and registers in this arrangement consumes a large silicon area.
Accordingly, a need exists for a technique for generating CRT timing signals that consumes less area than traditional techniques.
The present invention meets this need and provides aspects for generating CRT timing signals in a graphics accelerator. A method aspect includes shifting reference count values forward by a predetermined count period. A single comparator is utilized to perform a plurality of comparisons between CRT timing signals and at least one of the reference count values during the predetermined count period. Further, compensation for the shifting forward occurs by shifting back signals output from the single comparator.
With the present invention, CRT timing signals are generated through time-shifting of relevant signals. The time-shifting further allows the utilization of a single comparator, which reduces the logic gate requirement and thus the area and cost. These and other advantages of the present invention will be more fully understood in a conjunction with the following detailed description and accompanying drawings.